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? V OUT ? ? I ? ? ?
? ESR ? ?
8 ? C OUT ? f SW
Output Capacitor and V OUT Ripple
Table 1 suggests 0805 capacitors, but 0603 capacitors may
be used if space is at a premium. Due to voltage effects, the
0603 capacitors have a lower in-circuit capacitance, which
can degrade transient response and output ripple.
Increasing C OUT has a negligible effect on loop stability and
can be increased to reduce output voltage ripple or to
improve transient response. Output voltage ripple, ? V OUT , is:
? 1 ?
(8)
? ?
where C OUT is the effective output capacitance. The
capacitance of C OUT decreases at higher output voltages,
which results in higher ? V OUT . If large values are used for
C OUT , the regulator may fail to start under load. If an inductor
value greater than 1.0 ? H is used, at least 30 ? F of C OUT
should be used to ensure transient response performance.
The lowest ? V OUT is obtained when the IC is in PWM Mode
and, therefore, operating at 2.4 MHz. In PFM Mode, f SW is
reduced, causing ? V OUT to increase.
ESL Effects
The Equivalent Series Inductance (ESL) of the output
capacitor network should be kept low to minimize the square-
wave component of output ripple that results from the division
ratio C OUT ESL and the output inductor (L OUT ). The square-
wave component due to the ESL can be estimated as:
Layout Recommendations
The layout example below illustrates the recommended
component placement and top copper (green) routing. The
inductor in this example is the TDK VLC5020T-R47N.
To minimize VIN and SW spikes and thereby reduce voltage
stress on the IC’s power switches, it is critical to minimize the
loop length for the VIN bypass capacitors.
Switching current paths through C IN and C OUT should be
returned directly to the GND bumps of the IC on the top
layer of the printed circuit board (PCB). VOUT and GND
connections to the system power and ground planes can
be made through multiple vias placed as close as possible
to the C OUT capacitors. The regulator should be placed as
close to its load as possible to minimize trace inductance
and capacitance.
? V OUT ( SQ ) ? V IN ?
ESL COUT
L 1
(9)
A good practice to minimize this ripple is to use multiple
output capacitors to achieve the desired C OUT value. For
example, to obtain C OUT =20 ? F, a single 22 ? F 0805 would
produce twice the square wave ripple of two 10 ? F 0805.
To minimize ESL, try to use capacitors with the lowest ratio
of length to width. 0805s have lower ESL than 1206 s. If very
low output ripple is necessary, research vendors that
produce 0508 or 0612 capacitors with ultra-low ESL. Placing
additional small value capacitors near the load also reduces
the high-frequency ripple components.
Input Capacitor
The 10 ? F ceramic input capacitor should be placed as close
as possible between the VIN pin and PGND to minimize the
parasitic inductance. If a long wire is used to bring power to
the IC, additional “bulk” capacitance (electrolytic or tantalum)
should be placed between C IN and the power source lead to
reduce under-damped ringing that can occur between the
inductance of the power source leads and C IN .
The effective C IN capacitance value decreases as V IN
increases due to DC bias effects. This has no significant
impact on regulator performance.
To reduce ringing and overshoot on VIN and SW, an
additional bypass capacitor C IN1 is recommended. Because
this lower value capacitor has a higher resonant frequency
than C IN ; C IN1 should be placed closer to the VIN and GND
pins of the IC than C IN .
? 2011 Fairchild Semiconductor Corporation
FAN53540 ? Rev. 1.0.3
12
Figure 28. Recommended Layout
Connect the VOUT pin and R1 directly to C OUT using a low
impedance path (shown in red in Figure 28. Recommended
Layout). A >0.4 mm wide trace is recommended. Avoid
routing this trace directly beneath SW unless separated by
an internal GND plane.
If the MODE function is not required, extend the ground
plane through the MODE pin to reduce the loop inductance
for the VIN bypass.
Thermal Considerations
Heat is removed from the IC through the solder bumps to the
PCB copper. The junction-to-ambient thermal resistance
( ? JA ) is largely a function of the PCB layout (size, copper
weight, and trace width) and the temperature rise from
junction to ambient ( ? T).
For the FAN53540UC, ? JA is 38°C/W when mounted on its
four-layer evaluation board in still air, with 2 oz. outer layer
copper weight and 1 oz. inner layers. Halving the copper
thickness results in an increased ? JA of 48°C/W.
For long term reliable operation, the IC’s junction
temperature (T J ) should be maintained below 125°C.
Maximum IC power loss is 2.88 W. Figure 29 shows required
power dissipation and derating for a FAN53540UC mounted
on the Fairchild evaluation board in still air (38°C/W).
www.fairchildsemi.com
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